Nadesh Ramanathan

I am a PhD candidate in the Circuits and Systems Group at the Electrical and Electronic Engineering of Imperial College London and supervised by Professor George A. Constantinides. I am also co-supervised by Dr. John Wickerson. My PhD is supported and funded by the EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems (HiPEDS). Prior to the starting my PhD, I completed an MPhil in Advanced Computer Science at University of Cambridge.

My research interest is mainly focused on generating efficient digital computation on field-programmable gate arrays (FPGAs). I am particularly interested in the efficiency of high-level synthesis (HLS) for FPGAs. HLS automatically generate digital hardware from an algorithmic description using a high-level programming language, instead of lower-level RTL or schematic design. Currently, I am exploring efficient synthesis of C-based (OpenCL, C/C++) multi-threaded programs for FPGAs.


Nadesh Ramanathan
Department of Electrical and Electronic Engineering
Imperial College London
South Kensington Campus, London SW7 2BT
United Kingdom
Email: n_dot_ramanathan14_at_imperial_dot_ac_dot_uk
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