Nadesh Ramanathan

I am a PhD candidate in the Circuits and Systems Group at the Electrical and Electronic Engineering Department of Imperial College London, supervised by Professor George A. Constantinides and co-supervised by Dr. John Wickerson. My PhD is supported and funded by the EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems (HiPEDS). Prior to my PhD, I completed an MPhil in Advanced Computer Science at University of Cambridge.

My broad research interest is on designing efficient digital computation for field-programmable gate arrays (FPGAs). I am particularly interested in the efficiency of high-level synthesis (HLS) tools. HLS tools convert a high-level specification into digital hardware. Various high-level specifications are supported as inputs to HLS tools but the most common input is a C program. Describing hardware using C programs is attractive because it abstracts away low-level details of hardware design. Abstraction reduces the barrier-of-entry of software programmers with no hardware background and increases the productivity of hardware experts. Although C programs are a popular input, not all aspects of the C programming language are synthesisable. In my PhD, I explore the possibility and efficiency of synthesising multi-threaded C programs.


Nadesh Ramanathan
Department of Electrical and Electronic Engineering
Imperial College London
South Kensington Campus, London SW7 2BT
United Kingdom
Email: n_dot_ramanathan14_at_imperial_dot_ac_dot_uk
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